//*****************************************************************************
//
//  am_mcu_apollo510_otpinfo0.h
//
//*****************************************************************************

//*****************************************************************************
//
// Copyright (c) 2025, Ambiq Micro, Inc.
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its
// contributors may be used to endorse or promote products derived from this
// software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// This is part of revision release_sdk5p0p0-5f68a8286b of the AmbiqSuite Development Package.
//
//*****************************************************************************

#ifndef AM_REG_OTP_INFO0_H
#define AM_REG_OTP_INFO0_H

#define AM_REG_OTP_INFO0_BASEADDR 0x42004000

#define AM_REG_OTP_INFO0_SIGNATURE0_O 0x00000000
#define AM_REG_OTP_INFO0_SIGNATURE0_ADDR 0x42004000
#define AM_REG_OTP_INFO0_SIGNATURE1_O 0x00000004
#define AM_REG_OTP_INFO0_SIGNATURE1_ADDR 0x42004004
#define AM_REG_OTP_INFO0_SIGNATURE2_O 0x00000008
#define AM_REG_OTP_INFO0_SIGNATURE2_ADDR 0x42004008
#define AM_REG_OTP_INFO0_SIGNATURE3_O 0x0000000c
#define AM_REG_OTP_INFO0_SIGNATURE3_ADDR 0x4200400c
#define AM_REG_OTP_INFO0_BLRESET_O 0x00000010
#define AM_REG_OTP_INFO0_BLRESET_ADDR 0x42004010
#define AM_REG_OTP_INFO0_RESERVED_TRIM_O 0x00000014
#define AM_REG_OTP_INFO0_RESERVED_TRIM_ADDR 0x42004014
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_O 0x00000028
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_ADDR 0x42004028
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_O 0x0000002c
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_ADDR 0x4200402c
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG2_O 0x00000030
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG2_ADDR 0x42004030
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG3_O 0x00000034
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG3_ADDR 0x42004034
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG4_O 0x00000038
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG4_ADDR 0x42004038
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG5_O 0x0000003c
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG5_ADDR 0x4200403c
#define AM_REG_OTP_INFO0_SECURITY_VERSION_O 0x00000040
#define AM_REG_OTP_INFO0_SECURITY_VERSION_ADDR 0x42004040
#define AM_REG_OTP_INFO0_SECURITY_SRAM_RESV_O 0x00000044
#define AM_REG_OTP_INFO0_SECURITY_SRAM_RESV_ADDR 0x42004044
#define AM_REG_OTP_INFO0_SECURITY_RMAOVERRIDE_O 0x00000048
#define AM_REG_OTP_INFO0_SECURITY_RMAOVERRIDE_ADDR 0x42004048
#define AM_REG_OTP_INFO0_WIRED_TIMEOUT_O 0x00000054
#define AM_REG_OTP_INFO0_WIRED_TIMEOUT_ADDR 0x42004054
#define AM_REG_OTP_INFO0_SBR_SDCERT_ADDR_O 0x00000058
#define AM_REG_OTP_INFO0_SBR_SDCERT_ADDR_ADDR 0x42004058
#define AM_REG_OTP_INFO0_MAINPTR_O 0x00000060
#define AM_REG_OTP_INFO0_MAINPTR_ADDR 0x42004060
#define AM_REG_OTP_INFO0_CERTCHAINPTR_O 0x00000064
#define AM_REG_OTP_INFO0_CERTCHAINPTR_ADDR 0x42004064
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_O 0x00000068
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_ADDR 0x42004068
#define AM_REG_OTP_INFO0_NV_METADATA_OFFSET_O 0x0000006c
#define AM_REG_OTP_INFO0_NV_METADATA_OFFSET_ADDR 0x4200406c
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_O 0x00000070
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_ADDR 0x42004070
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_O 0x00000074
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_ADDR 0x42004074
#define AM_REG_OTP_INFO0_NV_CE_CMD_PINCFG_O 0x00000078
#define AM_REG_OTP_INFO0_NV_CE_CMD_PINCFG_ADDR 0x42004078
#define AM_REG_OTP_INFO0_NV_CLK_PINCFG_O 0x0000007c
#define AM_REG_OTP_INFO0_NV_CLK_PINCFG_ADDR 0x4200407c
#define AM_REG_OTP_INFO0_NV_DATA_PINCFG_O 0x00000080
#define AM_REG_OTP_INFO0_NV_DATA_PINCFG_ADDR 0x42004080
#define AM_REG_OTP_INFO0_NV_DQS_PINCFG_O 0x00000084
#define AM_REG_OTP_INFO0_NV_DQS_PINCFG_ADDR 0x42004084
#define AM_REG_OTP_INFO0_NV_CONFIG0_O 0x00000088
#define AM_REG_OTP_INFO0_NV_CONFIG0_ADDR 0x42004088
#define AM_REG_OTP_INFO0_NV_CONFIG1_O 0x0000008c
#define AM_REG_OTP_INFO0_NV_CONFIG1_ADDR 0x4200408c
#define AM_REG_OTP_INFO0_NV_CONFIG2_O 0x00000090
#define AM_REG_OTP_INFO0_NV_CONFIG2_ADDR 0x42004090
#define AM_REG_OTP_INFO0_NV_CONFIG3_O 0x00000094
#define AM_REG_OTP_INFO0_NV_CONFIG3_ADDR 0x42004094
#define AM_REG_OTP_INFO0_NV_OPTIONS_O 0x00000098
#define AM_REG_OTP_INFO0_NV_OPTIONS_ADDR 0x42004098
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_O 0x0000009c
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_ADDR 0x4200409c
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_O 0x000000a0
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_ADDR 0x420040a0

// SIGNATURE0 - Word 0 (low word, bits 31:0) of the 128-bit INFO0 signature.
#define AM_REG_OTP_INFO0_SIGNATURE0_SIG0_S 0
#define AM_REG_OTP_INFO0_SIGNATURE0_SIG0_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_SIGNATURE0_SIG0(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_SIGNATURE0_SIG0_Pos 0
#define AM_REG_OTP_INFO0_SIGNATURE0_SIG0_Msk 0xFFFFFFFF

// SIGNATURE1 - Word 1 (bits 63:32) of the 128-bit INFO0 signature.
#define AM_REG_OTP_INFO0_SIGNATURE1_SIG1_S 0
#define AM_REG_OTP_INFO0_SIGNATURE1_SIG1_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_SIGNATURE1_SIG1(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_SIGNATURE1_SIG1_Pos 0
#define AM_REG_OTP_INFO0_SIGNATURE1_SIG1_Msk 0xFFFFFFFF

// SIGNATURE2 - Word 2 (bits 95:64) of the 128-bit INFO0 signature.
#define AM_REG_OTP_INFO0_SIGNATURE2_SIG2_S 0
#define AM_REG_OTP_INFO0_SIGNATURE2_SIG2_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_SIGNATURE2_SIG2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_SIGNATURE2_SIG2_Pos 0
#define AM_REG_OTP_INFO0_SIGNATURE2_SIG2_Msk 0xFFFFFFFF

// SIGNATURE3 - Word 3 (high word, bits 127:96) of the 128-bit INFO0 signature.
#define AM_REG_OTP_INFO0_SIGNATURE3_SIG3_S 0
#define AM_REG_OTP_INFO0_SIGNATURE3_SIG3_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_SIGNATURE3_SIG3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_SIGNATURE3_SIG3_Pos 0
#define AM_REG_OTP_INFO0_SIGNATURE3_SIG3_Msk 0xFFFFFFFF

// BLRESET - This INFO0 register is required for RevB shadow loading (formerly known as SECURITY).
#define AM_REG_OTP_INFO0_BLRESET_SPINORSLEEPn_S 9
#define AM_REG_OTP_INFO0_BLRESET_SPINORSLEEPn_M 0x00000200
#define AM_REG_OTP_INFO0_BLRESET_SPINORSLEEPn(n) (((uint32_t)(n) << 9) & 0x00000200)
#define AM_REG_OTP_INFO0_BLRESET_SPINORSLEEPn_Pos 9
#define AM_REG_OTP_INFO0_BLRESET_SPINORSLEEPn_Msk 0x00000200
#define AM_ENUM_OTP_INFO0_BLRESET_SPINORSLEEPn_NORMALSLEEP      0x0  // Bootloader enters normal sleep.
#define AM_ENUM_OTP_INFO0_BLRESET_SPINORSLEEPn_SPIN             0x1  // Bootloader spins in an infinite while loop.

// RESERVED_TRIM - This is a reserved trim location. It defaults to 0x00000000 from the factory and must remain unchanged.
#define AM_REG_OTP_INFO0_RESERVED_TRIM_RSVD_TRIM_S 0
#define AM_REG_OTP_INFO0_RESERVED_TRIM_RSVD_TRIM_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_RESERVED_TRIM_RSVD_TRIM(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_RESERVED_TRIM_RSVD_TRIM_Pos 0
#define AM_REG_OTP_INFO0_RESERVED_TRIM_RSVD_TRIM_Msk 0xFFFFFFFF

// SECURITY_WIRED_IFC_CFG0 - This 32-bit word contains the interface configuration word0 for the UART wired update.
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD30_S 30
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD30_M 0xC0000000
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD30(n) (((uint32_t)(n) << 30) & 0xC0000000)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD30_Pos 30
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD30_Msk 0xC0000000
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_BAUDRATE_S 8
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_BAUDRATE_M 0x3FFFFF00
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_BAUDRATE(n) (((uint32_t)(n) << 8) & 0x3FFFFF00)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_BAUDRATE_Pos 8
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_BAUDRATE_Msk 0x3FFFFF00
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_DATALEN_S 6
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_DATALEN_M 0x000000C0
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_DATALEN(n) (((uint32_t)(n) << 6) & 0x000000C0)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_DATALEN_Pos 6
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_DATALEN_Msk 0x000000C0
#define AM_ENUM_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_DATALEN_5BIT  0x0  // 5 bit
#define AM_ENUM_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_DATALEN_6BIT  0x1  // 6 bit
#define AM_ENUM_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_DATALEN_7BIT  0x2  // 7 bit
#define AM_ENUM_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_DATALEN_8BIT  0x3  // 8 bit
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_2STOP_S 5
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_2STOP_M 0x00000020
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_2STOP(n) (((uint32_t)(n) << 5) & 0x00000020)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_2STOP_Pos 5
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_2STOP_Msk 0x00000020
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_EVEN_S 4
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_EVEN_M 0x00000010
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_EVEN(n) (((uint32_t)(n) << 4) & 0x00000010)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_EVEN_Pos 4
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_EVEN_Msk 0x00000010
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_PAR_S 3
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_PAR_M 0x00000008
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_PAR(n) (((uint32_t)(n) << 3) & 0x00000008)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_PAR_Pos 3
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_PAR_Msk 0x00000008
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_CTS_S 2
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_CTS_M 0x00000004
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_CTS(n) (((uint32_t)(n) << 2) & 0x00000004)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_CTS_Pos 2
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_CTS_Msk 0x00000004
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RTS_S 1
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RTS_M 0x00000002
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RTS(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RTS_Pos 1
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RTS_Msk 0x00000002
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD0_S 0
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD0_M 0x00000001
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD0(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD0_Pos 0
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG0_RSVD0_Msk 0x00000001

// SECURITY_WIRED_IFC_CFG1 - This 32-bit word contains the interface configuration word1 for the UART wired update.
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN3_S 24
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN3_M 0xFF000000
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN3(n) (((uint32_t)(n) << 24) & 0xFF000000)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN3_Pos 24
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN3_Msk 0xFF000000
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN2_S 16
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN2_M 0x00FF0000
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN2_Pos 16
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN2_Msk 0x00FF0000
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN1_S 8
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN1_M 0x0000FF00
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN1_Pos 8
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN1_Msk 0x0000FF00
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN0_S 0
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN0_M 0x000000FF
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN0(n) (((uint32_t)(n) << 0) & 0x000000FF)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN0_Pos 0
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG1_PIN0_Msk 0x000000FF

// SECURITY_WIRED_IFC_CFG2 - This 32-bit word contains the raw Pin configuration for the UART wired interface pin 0.
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG2_PINCFG_S 0
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG2_PINCFG_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG2_PINCFG(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG2_PINCFG_Pos 0
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG2_PINCFG_Msk 0xFFFFFFFF

// SECURITY_WIRED_IFC_CFG3 - This 32-bit word contains the raw Pin configuration for the UART wired interface pin 1.
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG3_PINCFG_S 0
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG3_PINCFG_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG3_PINCFG(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG3_PINCFG_Pos 0
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG3_PINCFG_Msk 0xFFFFFFFF

// SECURITY_WIRED_IFC_CFG4 - This 32-bit word contains the raw Pin configuration for the UART wired interface pin 2.
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG4_PINCFG_S 0
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG4_PINCFG_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG4_PINCFG(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG4_PINCFG_Pos 0
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG4_PINCFG_Msk 0xFFFFFFFF

// SECURITY_WIRED_IFC_CFG5 - This 32-bit word contains the raw Pin configuration for the UART wired interface pin 3.
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG5_PINCFG_S 0
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG5_PINCFG_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG5_PINCFG(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG5_PINCFG_Pos 0
#define AM_REG_OTP_INFO0_SECURITY_WIRED_IFC_CFG5_PINCFG_Msk 0xFFFFFFFF

// SECURITY_VERSION - This 32-bit word contains the version ID used for revision control
#define AM_REG_OTP_INFO0_SECURITY_VERSION_VERSION_S 0
#define AM_REG_OTP_INFO0_SECURITY_VERSION_VERSION_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_SECURITY_VERSION_VERSION(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_SECURITY_VERSION_VERSION_Pos 0
#define AM_REG_OTP_INFO0_SECURITY_VERSION_VERSION_Msk 0xFFFFFFFF

// SECURITY_SRAM_RESV - This 32-bit word indicates the minimum amount of DTCM that the Secure Boot Loader (SBL) reserves for the application, which will not be disturbed by SBL across a reset. The programmed value is rounded up, if necessary, by SBL to the next 256 byte boundary. That value is subtracted from the top of DTCM, resulting in a region at the top of DTCM that becomes the reserved area. Example: Apollo510 has 512KB of DTCM, 0x20000000-0x20007FFF. SECURITY_SRAM_RESV contains 0x3E8, SBL rounds up to 0x400, and reserves the region 0x20007C00 - 0x20007FFF for use by the application. Application data in this region will not be modified by SBL across resets.  The region will not be preserved across a POI reset or MRAM recovery operation.
#define AM_REG_OTP_INFO0_SECURITY_SRAM_RESV_SRAM_RESV_S 0
#define AM_REG_OTP_INFO0_SECURITY_SRAM_RESV_SRAM_RESV_M 0x000FFFFF
#define AM_REG_OTP_INFO0_SECURITY_SRAM_RESV_SRAM_RESV(n) (((uint32_t)(n) << 0) & 0x000FFFFF)
#define AM_REG_OTP_INFO0_SECURITY_SRAM_RESV_SRAM_RESV_Pos 0
#define AM_REG_OTP_INFO0_SECURITY_SRAM_RESV_SRAM_RESV_Msk 0x000FFFFF

// SECURITY_RMAOVERRIDE - Enables Ambiq to have the ability to download Ambiq RMA.
#define AM_REG_OTP_INFO0_SECURITY_RMAOVERRIDE_RSVD_ZERO_S 3
#define AM_REG_OTP_INFO0_SECURITY_RMAOVERRIDE_RSVD_ZERO_M 0xFFFFFFF8
#define AM_REG_OTP_INFO0_SECURITY_RMAOVERRIDE_RSVD_ZERO(n) (((uint32_t)(n) << 3) & 0xFFFFFFF8)
#define AM_REG_OTP_INFO0_SECURITY_RMAOVERRIDE_RSVD_ZERO_Pos 3
#define AM_REG_OTP_INFO0_SECURITY_RMAOVERRIDE_RSVD_ZERO_Msk 0xFFFFFFF8
#define AM_REG_OTP_INFO0_SECURITY_RMAOVERRIDE_OVERRIDE_S 0
#define AM_REG_OTP_INFO0_SECURITY_RMAOVERRIDE_OVERRIDE_M 0x00000007
#define AM_REG_OTP_INFO0_SECURITY_RMAOVERRIDE_OVERRIDE(n) (((uint32_t)(n) << 0) & 0x00000007)
#define AM_REG_OTP_INFO0_SECURITY_RMAOVERRIDE_OVERRIDE_Pos 0
#define AM_REG_OTP_INFO0_SECURITY_RMAOVERRIDE_OVERRIDE_Msk 0x00000007
#define AM_ENUM_OTP_INFO0_SECURITY_RMAOVERRIDE_OVERRIDE_ENABLE  0x2  // Enables override.

// WIRED_TIMEOUT - Holds the timeout value for wired transfers (in milliseconds).
#define AM_REG_OTP_INFO0_WIRED_TIMEOUT_TIMEOUT_S 0
#define AM_REG_OTP_INFO0_WIRED_TIMEOUT_TIMEOUT_M 0x0000FFFF
#define AM_REG_OTP_INFO0_WIRED_TIMEOUT_TIMEOUT(n) (((uint32_t)(n) << 0) & 0x0000FFFF)
#define AM_REG_OTP_INFO0_WIRED_TIMEOUT_TIMEOUT_Pos 0
#define AM_REG_OTP_INFO0_WIRED_TIMEOUT_TIMEOUT_Msk 0x0000FFFF

// SBR_SDCERT_ADDR - Location where bootloader will find SD certificates. Customer configures this based on the memory layout.
#define AM_REG_OTP_INFO0_SBR_SDCERT_ADDR_ICV_S 0
#define AM_REG_OTP_INFO0_SBR_SDCERT_ADDR_ICV_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_SBR_SDCERT_ADDR_ICV(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_SBR_SDCERT_ADDR_ICV_Pos 0
#define AM_REG_OTP_INFO0_SBR_SDCERT_ADDR_ICV_Msk 0xFFFFFFFF

// MAINPTR - Pointer to the main OEM image when Secure Boot is disabled.
#define AM_REG_OTP_INFO0_MAINPTR_ADDRESS_S 0
#define AM_REG_OTP_INFO0_MAINPTR_ADDRESS_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_MAINPTR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_MAINPTR_ADDRESS_Pos 0
#define AM_REG_OTP_INFO0_MAINPTR_ADDRESS_Msk 0xFFFFFFFF

// CERTCHAINPTR - Pointer to OEM certificate chain when Secure Boot is enabled.
#define AM_REG_OTP_INFO0_CERTCHAINPTR_ADDRESS_S 0
#define AM_REG_OTP_INFO0_CERTCHAINPTR_ADDRESS_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_CERTCHAINPTR_ADDRESS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_CERTCHAINPTR_ADDRESS_Pos 0
#define AM_REG_OTP_INFO0_CERTCHAINPTR_ADDRESS_Msk 0xFFFFFFFF

// MRAM_RCVY_CTRL - MRAM recovery master enable and enables for recovery types and GPIO pins for status and initiation.
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_MRAM_RCVY_EN_S 28
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_MRAM_RCVY_EN_M 0xF0000000
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_MRAM_RCVY_EN(n) (((uint32_t)(n) << 28) & 0xF0000000)
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_MRAM_RCVY_EN_Pos 28
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_MRAM_RCVY_EN_Msk 0xF0000000
#define AM_ENUM_OTP_INFO0_MRAM_RCVY_CTRL_MRAM_RCVY_EN_M_ENABLE  0x6  // Enables override, other vales = disabled.
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_RCVY_INPROGRESS_S 20
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_RCVY_INPROGRESS_M 0x0FF00000
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_RCVY_INPROGRESS(n) (((uint32_t)(n) << 20) & 0x0FF00000)
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_RCVY_INPROGRESS_Pos 20
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_RCVY_INPROGRESS_Msk 0x0FF00000
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_EMMC_PARTITION_S 18
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_EMMC_PARTITION_M 0x000C0000
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_EMMC_PARTITION(n) (((uint32_t)(n) << 18) & 0x000C0000)
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_EMMC_PARTITION_Pos 18
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_EMMC_PARTITION_Msk 0x000C0000
#define AM_ENUM_OTP_INFO0_MRAM_RCVY_CTRL_EMMC_PARTITION_USER    0x0  // Specifies the eMMC USER partition.
#define AM_ENUM_OTP_INFO0_MRAM_RCVY_CTRL_EMMC_PARTITION_BOOT1   0x1  // Specifies the eMMC BOOT1 partition.
#define AM_ENUM_OTP_INFO0_MRAM_RCVY_CTRL_EMMC_PARTITION_BOOT2   0x2  // Specifies the eMMC BOOT2 partition.
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_WD_EN_S 17
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_WD_EN_M 0x00020000
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_WD_EN(n) (((uint32_t)(n) << 17) & 0x00020000)
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_WD_EN_Pos 17
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_WD_EN_Msk 0x00020000
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_CTRL_POL_S 16
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_CTRL_POL_M 0x00010000
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_CTRL_POL(n) (((uint32_t)(n) << 16) & 0x00010000)
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_CTRL_POL_Pos 16
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_CTRL_POL_Msk 0x00010000
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_CTRL_PIN_S 8
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_CTRL_PIN_M 0x0000FF00
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_CTRL_PIN(n) (((uint32_t)(n) << 8) & 0x0000FF00)
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_CTRL_PIN_Pos 8
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_GPIO_CTRL_PIN_Msk 0x0000FF00
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_APP_RCVY_REBOOT_S 7
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_APP_RCVY_REBOOT_M 0x00000080
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_APP_RCVY_REBOOT(n) (((uint32_t)(n) << 7) & 0x00000080)
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_APP_RCVY_REBOOT_Pos 7
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_APP_RCVY_REBOOT_Msk 0x00000080
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_NV_RCVY_TYPE_S 4
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_NV_RCVY_TYPE_M 0x00000070
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_NV_RCVY_TYPE(n) (((uint32_t)(n) << 4) & 0x00000070)
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_NV_RCVY_TYPE_Pos 4
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_NV_RCVY_TYPE_Msk 0x00000070
#define AM_ENUM_OTP_INFO0_MRAM_RCVY_CTRL_NV_RCVY_TYPE_NV_OFF    0x0  // Non-volatile MRAM recovery disabled
#define AM_ENUM_OTP_INFO0_MRAM_RCVY_CTRL_NV_RCVY_TYPE_NV_MSPI   0x1  // MRAM Recovery using off-board MSPI device
#define AM_ENUM_OTP_INFO0_MRAM_RCVY_CTRL_NV_RCVY_TYPE_NV_EMMC   0x2  // MRAM Recovery using off-board EMMC device
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_NV_MODULE_NUM_S 2
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_NV_MODULE_NUM_M 0x0000000C
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_NV_MODULE_NUM(n) (((uint32_t)(n) << 2) & 0x0000000C)
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_NV_MODULE_NUM_Pos 2
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_NV_MODULE_NUM_Msk 0x0000000C
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_WIRED_RCVY_EN_S 1
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_WIRED_RCVY_EN_M 0x00000002
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_WIRED_RCVY_EN(n) (((uint32_t)(n) << 1) & 0x00000002)
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_WIRED_RCVY_EN_Pos 1
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_WIRED_RCVY_EN_Msk 0x00000002
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_APP_RCVY_EN_S 0
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_APP_RCVY_EN_M 0x00000001
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_APP_RCVY_EN(n) (((uint32_t)(n) << 0) & 0x00000001)
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_APP_RCVY_EN_Pos 0
#define AM_REG_OTP_INFO0_MRAM_RCVY_CTRL_APP_RCVY_EN_Msk 0x00000001

// NV_METADATA_OFFSET - Offset to the meta-data in the selected NV device. The meta-data supplies the offsets/sizes of the recovery images.  The Metadata is a 4 word "file" stored on the NV device, with the offset and size (in that order) for the SBL recovery image and OEMs recovery image (in that order). For EMMC devices the offset is a block offset, for MSPI it is a byte offset.
#define AM_REG_OTP_INFO0_NV_METADATA_OFFSET_META_OFFSET_S 0
#define AM_REG_OTP_INFO0_NV_METADATA_OFFSET_META_OFFSET_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_NV_METADATA_OFFSET_META_OFFSET(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_NV_METADATA_OFFSET_META_OFFSET_Pos 0
#define AM_REG_OTP_INFO0_NV_METADATA_OFFSET_META_OFFSET_Msk 0xFFFFFFFF

// NV_PWR_RESET_CFG - MRAM recovery NV device power and reset types, polarity and timing configurations
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_JEDEC_RESET_S 30
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_JEDEC_RESET_M 0x40000000
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_JEDEC_RESET(n) (((uint32_t)(n) << 30) & 0x40000000)
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_JEDEC_RESET_Pos 30
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_JEDEC_RESET_Msk 0x40000000
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_POL_S 29
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_POL_M 0x20000000
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_POL(n) (((uint32_t)(n) << 29) & 0x20000000)
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_POL_Pos 29
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_POL_Msk 0x20000000
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_DLY_UNITS_S 28
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_DLY_UNITS_M 0x10000000
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_DLY_UNITS(n) (((uint32_t)(n) << 28) & 0x10000000)
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_DLY_UNITS_Pos 28
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_DLY_UNITS_Msk 0x10000000
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_DLY_S 16
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_DLY_M 0x0FFF0000
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_DLY(n) (((uint32_t)(n) << 16) & 0x0FFF0000)
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_DLY_Pos 16
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_RESET_DLY_Msk 0x0FFF0000
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_POL_S 13
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_POL_M 0x00002000
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_POL(n) (((uint32_t)(n) << 13) & 0x00002000)
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_POL_Pos 13
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_POL_Msk 0x00002000
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_DLY_UNITS_S 12
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_DLY_UNITS_M 0x00001000
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_DLY_UNITS(n) (((uint32_t)(n) << 12) & 0x00001000)
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_DLY_UNITS_Pos 12
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_DLY_UNITS_Msk 0x00001000
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_DLY_S 0
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_DLY_M 0x00000FFF
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_DLY(n) (((uint32_t)(n) << 0) & 0x00000FFF)
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_DLY_Pos 0
#define AM_REG_OTP_INFO0_NV_PWR_RESET_CFG_PWR_DLY_Msk 0x00000FFF

// NV_PIN_NUMS - MRAM recovery NV device pin numbers Power, Reset and CE pins. The CE pin number is applicable to MSPI type only.  Pin numbers for the Data pins, SCLK and DQS (MSPI) and CMD (EMMC) are predetermined and set based on the device type (MSPI/EMMC) and the module number.
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_CE_PIN_S 16
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_CE_PIN_M 0x00FF0000
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_CE_PIN(n) (((uint32_t)(n) << 16) & 0x00FF0000)
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_CE_PIN_Pos 16
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_CE_PIN_Msk 0x00FF0000
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_RESET_PIN_S 8
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_RESET_PIN_M 0x0000FF00
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_RESET_PIN(n) (((uint32_t)(n) << 8) & 0x0000FF00)
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_RESET_PIN_Pos 8
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_RESET_PIN_Msk 0x0000FF00
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_PWR_PIN_S 0
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_PWR_PIN_M 0x000000FF
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_PWR_PIN(n) (((uint32_t)(n) << 0) & 0x000000FF)
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_PWR_PIN_Pos 0
#define AM_REG_OTP_INFO0_NV_PIN_NUMS_PWR_PIN_Msk 0x000000FF

// NV_CE_CMD_PINCFG - Pin config for the CE pin (MSPI) or CMD and D0 pins (EMMC) for MRAM recovery device. For EMMC devices the FNCSELxx field is ignored and set automatically based on the EMMC module number specified.
#define AM_REG_OTP_INFO0_NV_CE_CMD_PINCFG_CE_CMD_PINCGF_S 0
#define AM_REG_OTP_INFO0_NV_CE_CMD_PINCFG_CE_CMD_PINCGF_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_NV_CE_CMD_PINCFG_CE_CMD_PINCGF(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_NV_CE_CMD_PINCFG_CE_CMD_PINCGF_Pos 0
#define AM_REG_OTP_INFO0_NV_CE_CMD_PINCFG_CE_CMD_PINCGF_Msk 0xFFFFFFFF

// NV_CLK_PINCFG - The configuration to be written to the PINCFG register for the CLK pin for MRAM recovery. This applies to both MSPI and EMMC device types.  For EMMC devices the FNCSELxx field is ignored and set automatically based on the EMMC module number specified.
#define AM_REG_OTP_INFO0_NV_CLK_PINCFG_CLK_PINCGF_S 0
#define AM_REG_OTP_INFO0_NV_CLK_PINCFG_CLK_PINCGF_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_NV_CLK_PINCFG_CLK_PINCGF(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_NV_CLK_PINCFG_CLK_PINCGF_Pos 0
#define AM_REG_OTP_INFO0_NV_CLK_PINCFG_CLK_PINCGF_Msk 0xFFFFFFFF

// NV_DATA_PINCFG - The configuration to be written to the PINCFG register for the device's data pins. This applies to both MSPI and EMMC device types.  For EMMC devices the FNCSELxx field is ignored and set automatically based on the EMMC module number specified.
#define AM_REG_OTP_INFO0_NV_DATA_PINCFG_DATA_PINCFG_S 0
#define AM_REG_OTP_INFO0_NV_DATA_PINCFG_DATA_PINCFG_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_NV_DATA_PINCFG_DATA_PINCFG(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_NV_DATA_PINCFG_DATA_PINCFG_Pos 0
#define AM_REG_OTP_INFO0_NV_DATA_PINCFG_DATA_PINCFG_Msk 0xFFFFFFFF

// NV_DQS_PINCFG - The configuration to be written to the PINCFG register for the DQS pin in the MRAM recovery device. For EMMC devices this is not used.
#define AM_REG_OTP_INFO0_NV_DQS_PINCFG_DQS_PINCGF_S 0
#define AM_REG_OTP_INFO0_NV_DQS_PINCFG_DQS_PINCGF_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_NV_DQS_PINCFG_DQS_PINCGF(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_NV_DQS_PINCFG_DQS_PINCGF_Pos 0
#define AM_REG_OTP_INFO0_NV_DQS_PINCFG_DQS_PINCGF_Msk 0xFFFFFFFF

// NV_CONFIG0 - Device specific configuration used to configure the MRAM recovery NV device. For an MSPI device this value is written directly to the specified module's DEV0CFG register (Refer to the specified MSPI register for field definitions). For an EMMC device this location specifies the target clock frequency in Hz.  Note: For MSPI devices the field DEVCFG0 (in DEV0CFG) specifies which CEx (0/1) pin to use.  Only SERIALx, DUALx, QUADx and OCTALx are supported, QUAD_PAIRED, QUADPAIRED_SERIAL, and HEXx are not.
#define AM_REG_OTP_INFO0_NV_CONFIG0_CONFIG0_S 0
#define AM_REG_OTP_INFO0_NV_CONFIG0_CONFIG0_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_NV_CONFIG0_CONFIG0(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_NV_CONFIG0_CONFIG0_Pos 0
#define AM_REG_OTP_INFO0_NV_CONFIG0_CONFIG0_Msk 0xFFFFFFFF
#define AM_ENUM_OTP_INFO0_NV_CONFIG0_CONFIG0_EMMC_CLOCK_48MHZ   0x2DC6C00  // For eMMC devices, selects a target frequency of 48MHz.

// NV_CONFIG1 - Device specific configuration used to configure the MRAM recovery NV device. For a MSPI device this value is written directly to the specified module's DEV0CFG1 register.  For an EMMC device this location specifies the UHS mode - as specified in the UHSMODESEL field in REG_SDIO0_AUTO register.  Refer to the specified MSPI and SDIO registers for the specific field definitions.
#define AM_REG_OTP_INFO0_NV_CONFIG1_CONFIG1_S 0
#define AM_REG_OTP_INFO0_NV_CONFIG1_CONFIG1_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_NV_CONFIG1_CONFIG1(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_NV_CONFIG1_CONFIG1_Pos 0
#define AM_REG_OTP_INFO0_NV_CONFIG1_CONFIG1_Msk 0xFFFFFFFF
#define AM_ENUM_OTP_INFO0_NV_CONFIG1_CONFIG1_EMMC_HOST_UHS_SDR120x0  // For eMMC devices, selects the UHS mode EMMC_HOST_UHS_SDR12. This is generally the default mode.
#define AM_ENUM_OTP_INFO0_NV_CONFIG1_CONFIG1_EMMC_HOST_UHS_SDR250x1  // For eMMC devices, selects the UHS mode EMMC_HOST_UHS_SDR25.
#define AM_ENUM_OTP_INFO0_NV_CONFIG1_CONFIG1_EMMC_HOST_UHS_SDR500x2  // For eMMC devices, selects the UHS mode EMMC_HOST_UHS_SDR50.
#define AM_ENUM_OTP_INFO0_NV_CONFIG1_CONFIG1_EMMC_HOST_UHS_SDR1040x3  // For eMMC devices, selects the UHS mode EMMC_HOST_UHS_SDR104.
#define AM_ENUM_OTP_INFO0_NV_CONFIG1_CONFIG1_EMMC_HOST_UHS_DDR500x4  // For eMMC devices, selects the UHS mode EMMC_HOST_UHS_DDR50.

// NV_CONFIG2 - Device specific configuration used to configure the MRAM recovery NV device. For a MSPI device this value is written directly to the specified module's DEV0DDR register. (Refer to the specified MSPI register for field definitions). For an EMMC device this location is unused.
#define AM_REG_OTP_INFO0_NV_CONFIG2_CONFIG2_S 0
#define AM_REG_OTP_INFO0_NV_CONFIG2_CONFIG2_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_NV_CONFIG2_CONFIG2(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_NV_CONFIG2_CONFIG2_Pos 0
#define AM_REG_OTP_INFO0_NV_CONFIG2_CONFIG2_Msk 0xFFFFFFFF

// NV_CONFIG3 - Device specific configuration used to configure the MRAM recovery NV device. For a MSPI device this value is written directly to the specified module's DEV0SCRAMBLING register.(Refer to the specified MSPI register for field definitions). For an EMMC device this location is unused.
#define AM_REG_OTP_INFO0_NV_CONFIG3_CONFIG3_S 0
#define AM_REG_OTP_INFO0_NV_CONFIG3_CONFIG3_M 0xFFFFFFFF
#define AM_REG_OTP_INFO0_NV_CONFIG3_CONFIG3(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
#define AM_REG_OTP_INFO0_NV_CONFIG3_CONFIG3_Pos 0
#define AM_REG_OTP_INFO0_NV_CONFIG3_CONFIG3_Msk 0xFFFFFFFF

// NV_OPTIONS - Device specific options for the selected MRAM recovery device type.  Each field is used only for the device type specified (EMMC or MSPI) and is unused and ignored when not configured for the specified type.  Refer to the specified MSPI/EMMC registers for further information of the specific register and field's usage.
#define AM_REG_OTP_INFO0_NV_OPTIONS_EMMC_BUS_WIDTH_S 28
#define AM_REG_OTP_INFO0_NV_OPTIONS_EMMC_BUS_WIDTH_M 0x70000000
#define AM_REG_OTP_INFO0_NV_OPTIONS_EMMC_BUS_WIDTH(n) (((uint32_t)(n) << 28) & 0x70000000)
#define AM_REG_OTP_INFO0_NV_OPTIONS_EMMC_BUS_WIDTH_Pos 28
#define AM_REG_OTP_INFO0_NV_OPTIONS_EMMC_BUS_WIDTH_Msk 0x70000000
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_EMMC_BUS_WIDTH_EMMC1       0x0  // 1-bit transfers
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_EMMC_BUS_WIDTH_EMMC4       0x2  // 4-bit transfers
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_EMMC_BUS_WIDTH_EMMC8       0x3  // 8-bit transfers
#define AM_REG_OTP_INFO0_NV_OPTIONS_EMMC_VOLTAGE_S 26
#define AM_REG_OTP_INFO0_NV_OPTIONS_EMMC_VOLTAGE_M 0x0C000000
#define AM_REG_OTP_INFO0_NV_OPTIONS_EMMC_VOLTAGE(n) (((uint32_t)(n) << 26) & 0x0C000000)
#define AM_REG_OTP_INFO0_NV_OPTIONS_EMMC_VOLTAGE_Pos 26
#define AM_REG_OTP_INFO0_NV_OPTIONS_EMMC_VOLTAGE_Msk 0x0C000000
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_EMMC_VOLTAGE_RSVD          0x0  // Unused, reserved
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_EMMC_VOLTAGE_EMMCV18       0x1  // 1.8v I/O
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_EMMC_VOLTAGE_EMMCV30       0x2  // 3.0v I/O
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_EMMC_VOLTAGE_EMMCV33       0x3  // 3.3v I/O
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_READ_CLKSEL_S 20
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_READ_CLKSEL_M 0x00F00000
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_READ_CLKSEL(n) (((uint32_t)(n) << 20) & 0x00F00000)
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_READ_CLKSEL_Pos 20
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_READ_CLKSEL_Msk 0x00F00000
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_WIDTHS_S 16
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_WIDTHS_M 0x000F0000
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_WIDTHS(n) (((uint32_t)(n) << 16) & 0x000F0000)
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_WIDTHS_Pos 16
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_WIDTHS_Msk 0x000F0000
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CLKSEL_S 12
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CLKSEL_M 0x0000F000
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CLKSEL(n) (((uint32_t)(n) << 12) & 0x0000F000)
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CLKSEL_Pos 12
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CLKSEL_Msk 0x0000F000
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_S 8
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_M 0x00000F00
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL(n) (((uint32_t)(n) << 8) & 0x00000F00)
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_Pos 8
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_Msk 0x00000F00
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_None 0x0  // No Pre-CMDs are sent. The first MSPI command to the device will be the command contained in the MSPI_READCMD.
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_Cxxx 0x1  // One single byte command (PCMD1=CMD1)
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_CCxx 0x2  // Two commands (PCMD1=CMD1, and PCMD2=CMD2)
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_CDxx 0x3  // One command with one data byte for the command (PCMD1=CMD1, and PCMD2=DATA)
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_CCCx 0x4  // Three single byte commands (PCMD1=CMD1, PCMD2=CMD2 and PCMD3=CMD3)
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_CCDx 0x5  // Two CMDs, with one data byte following the second command (PCMD1=CMD1, PCMD2=CMD2, PCMD3=DATA)
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_CDCx 0x6  // Two CMDs, with one data byte following the first command (PCMD1=CMD1, PCMD2=DATA, PCMD3=CMD2)
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_CDDx 0x7  // One CMD, with two data bytes following the first command (PCMD1=CMD1, PCMD2=DATA, PCMD3=DATA)
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_CCCC 0x8  // Four single byte commands (PCMD1=CMD1, PCMD2=CMD2, PCMD3=CMD3, PCMD4=CMD4)
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_CCCD 0x9  // Three commands with one data byte following the third command (PCMD1=CMD1, PCMD2=CMD2, PCMD3=CMD3, PCMD4=DATA)
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_CCDC 0xA  // Three commands with one data byte following the second command (PCMD1=CMD1, PCMD2=CMD2, PCMD3=DATA, PCMD4=CMD3)
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_CDCC 0xB  // Three commands with one data byte following the first command (PCMD1=CMD1, PCMD2=DATA, PCMD3=CMD2, PCMD4=CMD3)
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_CDCD 0xC  // Two commands with one data byte following the each command (PCMD1=CMD1, PCMD2=DATA, PCMD3=CMD2, PCMD4=DATA)
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_CCDD 0xD  // Two commands with two data bytes following the second command (PCMD1=CMD1, PCMD2=CMD2, PCMD3=DATA, PCMD4=DATA)
#define AM_ENUM_OTP_INFO0_NV_OPTIONS_MSPI_PRECMD_CTRL_PCMD_CDDC 0xE  // Two commands with two data bytes following the first command (PCMD1=CMD1, PCMD2=DATA, PCMD3=DATA, PCMD4=CMD2)
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_READCMD_S 0
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_READCMD_M 0x000000FF
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_READCMD(n) (((uint32_t)(n) << 0) & 0x000000FF)
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_READCMD_Pos 0
#define AM_REG_OTP_INFO0_NV_OPTIONS_MSPI_READCMD_Msk 0x000000FF

// NV_MSPI_PRECMDS - Pre-Commands sent prior to the Read command that loads the recovery image(s) for MSPI NV devices. How the four PCMDx fields are used is controlled by MSPI_PRECMD_CTRL the NV_OPTIONS word. Each command is sent followed by the delay time specified in the RESET_DLY and RESET_DLY_UNITS fields in the NV_OPTIONS word. The clock speed used to send the pre-commands is specified in the MSPI_PRECMD_CLKSEL field also in the NV_OPTIONS word.
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD1_S 24
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD1_M 0xFF000000
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD1(n) (((uint32_t)(n) << 24) & 0xFF000000)
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD1_Pos 24
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD1_Msk 0xFF000000
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD2_S 16
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD2_M 0x00FF0000
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD2_Pos 16
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD2_Msk 0x00FF0000
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD3_S 8
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD3_M 0x0000FF00
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD3(n) (((uint32_t)(n) << 8) & 0x0000FF00)
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD3_Pos 8
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD3_Msk 0x0000FF00
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD4_S 0
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD4_M 0x000000FF
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD4(n) (((uint32_t)(n) << 0) & 0x000000FF)
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD4_Pos 0
#define AM_REG_OTP_INFO0_NV_MSPI_PRECMDS_PCMD4_Msk 0x000000FF

// MRAM_RCV_RETRIES_TIMES - The number of retries if MRAM recovery fails and the times between retries.
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MAX_RETRIES_S 16
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MAX_RETRIES_M 0xFFFF0000
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MAX_RETRIES(n) (((uint32_t)(n) << 16) & 0xFFFF0000)
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MAX_RETRIES_Pos 16
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MAX_RETRIES_Msk 0xFFFF0000
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MIN_RETRY_TIME_S 8
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MIN_RETRY_TIME_M 0x0000FF00
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MIN_RETRY_TIME(n) (((uint32_t)(n) << 8) & 0x0000FF00)
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MIN_RETRY_TIME_Pos 8
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MIN_RETRY_TIME_Msk 0x0000FF00
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MAX_RETRY_TIME_S 0
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MAX_RETRY_TIME_M 0x000000FF
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MAX_RETRY_TIME(n) (((uint32_t)(n) << 0) & 0x000000FF)
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MAX_RETRY_TIME_Pos 0
#define AM_REG_OTP_INFO0_MRAM_RCV_RETRIES_TIMES_MAX_RETRY_TIME_Msk 0x000000FF

#endif
